1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a technology for an LD (Lateral Double Diffused) MOS transistor as a high voltage element employed in a liquid crystal driving IC, etc., for example.
2. Related Art of the Invention
In the LDMOS transistor structure, a new diffusion region is formed by diffusing a different conductivity type impurity into a diffusion region formed on the surface side of a semiconductor substrate, and then a difference in lateral diffusion lengths of these diffusion regions is utilized as an effective channel length. Thus, since a short channel can be formed, the LDMOS transistor is suitable for the low ON-resistance device.
FIG. 18 is a sectional view showing the LDMOS transistor in the prior art. The N-channel LDMOS transistor structure is shown as an example. In this case, although explanation of the P-channel LDMOS transistor structure is omitted, it is well known that the P-channel LDMOS transistor structure has the similar structure except for the different conductivity type.
In FIG. 18, 1 denotes one conductivity type, e.g., P-type semiconductor substrate, and 2 denotes an N-type well region. A P-type body region 3 is formed in the N-type well region 2, and then an N-type diffusion region 4 is formed in the P-type body region 3. An N-type diffusion region 5 is also formed in the N-type well region 2. A gate electrode 7 is formed on a gate insulating film 6 on the surface of the substrate. A channel region 8 is formed on a surface region of the P-type body region 3 immediately below the gate electrode 7.
Then, the N-type diffusion region 4 acts as a source region, the N-type diffusion region 5 acts as a drain region, and the N-type well region 2 located under a LOCOS oxide film 9A acts as a drift region. Then, 10 and 11 denote a source electrode and a drain electrode respectively, 12 denotes a P-type diffusion region for supplying the potential to the P-type body region 3, and 13 denotes an interlayer insulating film.
In the above LDMOS transistor, since the N-type well region 2 is formed by diffusing the impurity, the impurity concentration of the surface of the N-type well region 2 is increased. Thus, the current is ready to flow through the surface of the N-type well region 2, and also the higher breakdown voltage can be achieved. Then, the LDMOS transistor having such configuration is called a REduced SRface (RESURF) type LDMOS, and a dopant concentration in the drift region of the N-type well region 2 is set to satisfy RESURF conditions. Such technology is disclosed in JPA (Patent Application Publication (KOKAI) Hei) 9-139438, etc.
However, as shown in FIG. 18, since the N-type well region 2 is formed uniformly up to the same depth position, it prevents the higher breakdown voltage and the reduction in ON-resistance.
In addition, as shown in FIG. 20, in the case that a plurality of LDMOS transistors having the above structure are arranged via a element isolation film 9B, the element isolation films 9B to isolate the adjacent transistors are increased in size to thus prevent the higher integration. In other words, the N-type well regions 2 which are positioned adjacently via the element isolation film 9B have the large lateral spread since they are formed by the well-known well diffusion step, and also the depletion layer widely spreads. Hence, the element isolation film 9B needs an L2 (about 10 μm to 30 μm) size, for example.
Further, as shown in FIG. 19A, there is provided a device constituted by the P-channel high breakdown voltage MOS transistor (Pch MOS Tr) and the N-channel LDMOS transistor (Nch DMOS Tr) as a CMOS circuit which can achieve the high breakdown voltage. In this case, as shown in FIG. 19B, in the P-channel high breakdown voltage MOS transistor, an N-type well region 51 is formed on a one conductivity type, e.g., P-type semiconductor substrate 1, then a gate electrode 57 is formed on a surface of the N-type well region 51 via a gate insulating film 56, then P-type low concentration diffusion regions 54A, 54B are formed on a substrate surface layer to be adjacent to the gate electrode 57, and then P-type high concentration diffusion regions 55A, 55B are formed in the P-type diffusion regions 54A, 54B. The P-type diffusion regions 54A, 55A act as a source region, and the P-type diffusion regions 54B, 55B act as a drain region.
Then, the CMOS structure is constructed by such P-channel high breakdown voltage MOS transistor and the foregoing N-channel LDMOS transistor.
However, in the CMOS structure in the prior art the process for manufacturing the N-channel LDMOS transistor cannot be sufficiently used.